1. Field of the Invention
This invention relates to the field of polishing semiconductor wafers in the fabrication of integrated circuits, and more particularly to the field of polishing semiconductor wafers in an overhanging relationship with a polishing surface.
2. Statement of the Problem
Integrated circuits are generally mass produced by fabricating hundreds of identical circuit patterns on a single semiconductor wafer that is subsequently divided into hundreds of identical dies or chips. While sometimes referred to as "semiconductor devices", integrated circuits are in fact fabricated from various materials that are either electrically conductive, non-conductive, or semiconductive. Silicon, the most commonly used semiconductor material, can be used in either the single crystal or polycrystalline form. Both forms of silicon may be made conductive by adding impurities to it, which is commonly referred to as "doping." Likewise it is common practice to modify other materials, such as conductors or insulators, by adding other components. Alternatively, one material, such as silicon, may be removed or replaced by another. Processes commonly used to modify, remove, or deposit a material are ion implantation, sputtering, etching, chemical vapor deposition (CVD) and variations thereof, such as plasma enhanced chemical vapor deposition (PECVD).
The above-discussed processes are often selectively applied to an integrated circuit through the use of a masking process. In the masking process, a photo-mask containing the pattern of the structure to be fabricated is created, and the wafer is coated with a light-sensitive material called photoresist or resist. Then, the resist-coated wafer is exposed to ultraviolet light through the photo-mask to soften or harden parts of the resist depending on whether positive or negative resist is used. Once the softened parts of the resist are removed, the wafer is treated by one of the processes discussed above to modify, remove, or replace the part unprotected by the resist, and then the remaining resist is stripped. This masking process permits specific areas of the integrated circuit to be modified, removed, or replaced.
These steps of deposition or removal are frequently followed by a planarization step such as chemical mechanical planarization (CMP). This planarization process helps to minimize barriers to multilayer formation and metallization, as well as to smooth, flatten, and clean the surface. This process involves chemically etching a surface while also mechanically grinding or polishing it. The combined action of surface chemical reaction and mechanical polishing allows for a controlled, layer by layer removal of a desired material from the wafer surface resulting in the preferential removal of protruding surface topography and a planarized wafer surface. In the past few years, CMP has become one of the most effective techniques for planarizing all or a portion of a semiconductor wafer.
In general, the CMP process involves holding a semiconductor substrate, such as a wafer, against a rotating wetted polishing pad under controlled downward pressure. A polishing slurry metered onto the polishing pad contains etchants and an abrasive material such as alumna or silica. A rotating wafer carrier is typically utilized to hold the wafer under controlled pressure against a rotating polishing platen covered with the polishing pad typically formed of a relatively soft material such as a felt fabric impregnated with blown polyurethane. The CMP process is well known (See, for example, U.S. Pat. No. 5,302,233 to Kim et al. and U.S. Patent Re. 34,425 to Schultz).
One problem associated with the CMP process is that the semiconductor wafer may be subjected to non-uniform planarization due to the relative velocity differential between the outer peripheral portions and the interior portions of the rotating wafer and due to the relative velocity differential between these portions of the wafer and the polishing pad. On a rotating disk, the linear velocity of a point along a radial line increases linearly with the distance from the center (the velocity of a point being equal to the angular velocity multiplied by the distance of the point from the center). It is known that the rate of material removal by a polishing surface from a workpiece is associated with the relative linear velocity between the points of contact between the two surfaces. For example, assuming that the polishing surface were stationary, the faster moving peripheral portions of the semiconductor wafer would experience a relatively larger rate of material removal than the relatively slower moving interior portions. This problem of uneven material removal would be accentuated if the polishing surface were rotated and the peripheral portion of the wafer and the peripheral portion of the rotating polishing surface coincided. Therefore, in order to insure a more consistent rate of polishing, it is advantageous to "overhang" the wafer with respect to the polishing surface so that the slower moving central portions of the wafer are exposed to the faster moving peripheral portions of the polishing surface, and, correspondingly, the faster moving peripheral portion of the wafer is exposed to the more central, slower moving portion of the polishing surface. The overhanging relationship of the wafer to the polishing pad results in a more consistent relative velocity between the points of contact between the wafer and polishing pad across the surface of the wafer. The problem of irregularities caused by inconsistent relative velocities across the surface of the wafer exists whether the polishing platen and wafer are rotated in the same direction or in opposite directions of rotation. The advantage of overhanging the wafer with respect to the polishing platen was discussed in U.S. Pat. No. 5,081,796 (Re. 34,425) to Schultz.
However, while the overhanging arrangement partially solves the problem of polishing irregularities due to the difference in the relative linear velocities, the overhanging arrangement creates a different problem. In many of the devices for polishing wafers, the wafer carrier has a slight angular rotation about an axis perpendicular to its primary axis of rotation. This rotation about an axis perpendicular to the primary axis of rotation is defined as "gimballing." When the center of gravity of the wafer and wafer carrier overhang the polishing pad, gravity will cause gimballing because the wafer is not evenly supported across its face. Furthermore, the outer periphery of the prior art polishing pad wears faster than the inner portion. This uneven wear at the periphery of the polishing pad further enhances and encourages gimballing.
Gimballing results in a lack of homogeneous planarization that can result in some material not being removed (i.e., under polishing), in some material being removed that was not intended to be removed (i.e., over polishing), or both. Further, since the subsequent processes assume or even require a planar wafer surface, this lack of planarization can alter the properties and parameters of the device. All of these results contribute to defective devices, loss of device yield, and lack of device reliability. Thus, there exists a need for apparatus and methods to improve the uniformity of planarization in the CMP process where the wafer is placed in an overhanging relationship with the polishing pad.
Generally, a change in one phase of the integrated fabrication process usually impacts other phases. Since integrated circuit fabrication processes are highly complex and require sophisticated equipment, developments of entirely new processes and materials can be quite costly. Thus, new apparatus and methods for control of the CMP process that can be incorporated into current fabrication technology would be highly desirable to avoid expensive modification of equipment and processes. Therefore, a need further exists to eliminate the problem of gimballing without substantially modifying the proven processes and equipment in place.
A cost effective solution is needed to provide support to the wafer in an overhanging position without significantly polishing the wafer in the region overhanging the polishing pad. One cost effective solution would be to design a polishing pad to provide support across the face of the wafer but which does not polish. Various designs exist for polishing pads. Exemplary of prior art polishing pads are the following U.S. Pat. No. 5,329,734 to Yu, U.S. Pat. No. 5,310,455 to Pasch et al., U.S. Pat. No. 5,257,478 to Hyde et al., U.S. Pat. No. 5,212,910 to Breivogel et al., U.S. Pat. No. 5,197,999 to Thomas. (See also Japanese Patent No. 6-97132). Only the Yu, U.S. Pat. No. 5,329,734, discloses a polishing pad specifically designed to compensate for the polishing nonuniformity caused by the difference in relative velocities between the edge of the wafer and the center of the wafer.
Yu discloses a polishing pad having a first region lying closer to the edge of the polishing pad and a second region lying closer to the center of polishing pad with a plurality of openings or pores larger than those of the first region. However, the polishing pad of Yu was not designed to be used in polishing a wafer in the overhanging position, and does not solve the problem of gimballing. Both regions of the Yu polishing pad were designed to polish the wafer, albeit at different rates.
None of these prior art pads provide a supporting surface of a material with low polishing characteristics around an interior polishing surface. Such a composite surface would prevent gimballing by supporting the entire surface of the wafer while still exploiting the advantages of the overhanging position without requiring extensive modifications to the existing equipment and processes.